LCD connections, TINI bus loading - some numbers
Stephen Early
steve@greenend.org.uk
Sat, 25 Nov 2000 14:37:53 +0000 (GMT)
On Friday, 24 Nov 2000, Bruce Boyes wrote:
> We use Vcc tied to LCD pin 15, then pin 16 pulled low through a 10 ohm
> resistor and a FET driver. You can provide a jumper to bypass the 10 ohms,
> since some LCDs have their own built in while others do not. If you provide
> parallel pulldowns (we use the TPIC6B273 for this, 8 x FETs each sinking at
> least 150 mA) then you can have a digital backlight brightness control.
> more important for battery operation than this player.
Ok, I'll put in something like this. I might even be able to find a
port pin somewhere to give software control of it, although I'm not
sure where from at the moment. (Perhaps re-task one of the 'LED'
outputs of the FPGA.)
> For contrast, some LCDs need a negative voltage. If you avoid those for
> simplicity, use a digital pot such as the DS1804. You need an opamp if you
> will drive negative, plus a negative supply which could be a tap off the
> charge pump of an RS232 driver, but be careful of the load.
Right. I can put in traces and jumpers to tap off the charge pump of
the MAX239 driver, but I doubt I'll ever test it. I like the
suggestion of using the DS1804 (which version, by the way?), but I'll
need to find an extra three control signals from somewhere...
> >There's another issue I'd like to ask advice on. At the moment I am
> >placing four loads on the TINI's databus: the FIFO, the FPGA, a bus
> >transceiver to isolate the databus from the LCDs, and the serial
> >controller. I have the option of hiding some of these loads behind the
> >bus transceiver - potentially all of them except the transceiver
> >itself. I'm thinking of putting the serial controller, and possibly
> >the FPGA, on the 'LCD' side of the transceiver. Any thoughts?
>
> Why not use the FPGA as a buffer? We just did that with our SBX2 board - a
> XC95108 CPLD is the glue and control logic, plus the bus buffer. It
> presents only one CMOS load to TINI, then. It also has an LCD interface
> which does the slower LCD timing. It also includes a keypad debouncer -
> maybe your FPGA already includes this.
I did originally use the FPGA as a buffer, but I ran out of pins
(using an EPM7128SLC-84). The FPGA pin assignments are currently as
follows:
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be
connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
----------------------------------------------------------------------------
CHIP "mp3glue" ASSIGNED TO AN EPM7128SLC84-7
fifo_data2 : 1
fifo_hf : 2
VCCINT : 3
fifo_data7 : 4
serial_int2 : 5
xwr : 6
GND : 7
switch1 : 8
a0 : 9
fifo_data6 : 10
fifo_data5 : 11
switch2 : 12
VCCIO : 13
TDI : 14
ce3 : 15
a16 : 16
a1 : 17
mp3_data_req : 18
GND : 19
a19 : 20
fifo_ff : 21
mp3_sck : 22
TMS : 23
fifo_data1 : 24
fifo_data3 : 25
VCCIO : 26
a6 : 27
extint : 28
lcdreg : 29
serial_int1 : 30
switch0 : 31
GND : 32
switch5 : 33
a3 : 34
leds3 : 35
leds5 : 36
xpsen : 37
VCCIO : 38
databus7 : 39
leds0 : 40
databus3 : 41
GND : 42
VCCINT : 43
leds2 : 44
leds1 : 45
fifo_reset : 46
GND : 47
bustransdir : 48
switch4 : 49
mp3_reset : 50
switch7 : 51
fifo_wr : 52
VCCIO : 53
lcde2 : 54
databus5 : 55
databus1 : 56
lcde1 : 57
serial_sel : 58
GND : 59
bustransgate : 60
switch6 : 61
TCK : 62
databus0 : 63
databus4 : 64
databus2 : 65
VCCIO : 66
databus6 : 67
leds6 : 68
leds4 : 69
leds7 : 70
TDO : 71
GND : 72
switch3 : 73
fifo_ef : 74
fifo_rd : 75
fifo_data0 : 76
mp3_bit_en : 77
VCCIO : 78
a5 : 79
RESERVED : 80
mp3_sdi : 81
GND : 82
CLK : 83
fifo_data4 : 84
I could reclaim some pins by supporting fewer status LEDs or input
switches, or possibly farming off those functions to other
devices. I think I could definitely get away with fewer LEDs - there
are eight provided for in the design at the moment. There's one spare
IO pin at the moment, too.
> I'd also recommend a reset circuit such as a TLC77C05 (I forget the exact
> number), to put TINI and all the parts of the system in reset below 4.75V
> and let them all wake up together. You don't want part of the system
> running before the others are ready.
There's not actually a lot that needs resetting on this board. The
TINI looks after itself, and all the other parts that need resetting
(primarily the MP3 decoder, and some internal parts of the glue logic)
are reset using the control register in the glue, on command from the
TINI.
>[TINI databus load characteristics]
> This does not include trace capacitance. So a worst-case component TINI 1
> MB now has 47pF on address (out of 80 allowed) and 70 pF on data (out of
> 100 allowed). PCBS add at least 10-12 pF per foot of trace as a rough
> estimate, so you can see that there is not a lot of extra drive ability on
> TINI. Add in 10 pF on each for board traces (TINI itself plus a socket
> board) and you have 20pF available on address and 20 pF on data, 2 CMOS
> loads to be conservative.
Ok, I'm convinced now. I will put two loads on the TINI databus: the
FPGA and the bus transceiver. On the other side of the transceiver
will be the FPGA, UART, and LCDs. (Unless there's a good reason for
providing extra buffering for the LCD connections.)
Thanks for the advice,
Steve Early